The present invention relates to an apparatus for picture decoding for decoding and/or decompressing coded and/or compressed picture signals and more particularly to an apparatus for picture decoding which is effective in reducing the memory capacity, the memory data bus width, the decoding delay time, and the decoding clock frequency.
An international standard of picture compression which is referred to as MPEG2 is being decided for the purpose of application to digital broadcasting and recording media (for example, the journal of the institute of television engineers of Japan, Vol. 48, No. 1, pp 44 to 49). In the MPEG2 coding system, picture signals are coded by combining an intra-frame coding frame (hereinafter called an I frame), an inter-frame coding frame (hereinafter called a P frame), and a frame-interpolation coding frame (hereinafter called a B frame) properly so as to enable coexistence of the high data compression rate and the random access and edit functions with each other.
In the I frame, only picture data in the frame is compressed by transform coding. This is a system using that there is a correlation between picture data in the frame, which divides the frame into blocks of the predetermined size, transforms each block, quantizes the coefficient data after conversion equivalent to the frequency component, and further generates coded data by variable length coding.
In the P frame, the data compression rate is increased by using a high correlation between the frames. The previous frame and the current frame are compared in the predetermined number of blocks, and a motion vector is obtained, and the picture data of the previous frame is read from the position shifted according to the motion vector, and a predicted value is obtained. Thereafter, the predicted value is subtracted from the picture data of the current frame to be coded, and this motion compensated prediction error is transform-coded in the same way as with the intra-frame coding system, and coded data is generated.
To increase the data compression rate more, the B frame is used. Frame-interpolation coding is also called bidirectional motion compensation inter-frame coding and uses the correlation not only with the previous frame but also with the subsequent frame. This system compares the previous frame in the order of display with the current frame in the predetermined number of blocks, obtains a motion vector, obtains a motion vector also for the subsequent frame in the order of display in the predetermined number of blocks at the same time, reads the picture data of the previous frame and the subsequent frame from the position shifted according to the respective motion vectors, generates a mean value, and obtains a frame-interpolation value. Thereafter, the system subtracts the frame-interpolation value from the picture data of the current frame to be coded and obtains a motion compensated prediction error.
For example, the system executes intra-frame coding for the first frame (I frame), executes inter-frame coding for the fourth frame using the first frame as a reference picture (P frame), and then executes frame-interpolation coding for the second and third frames using the first and fourth frames as a reference picture (B frame). In this case, the frame display order is the first&gt;the second&gt;the third&gt;the fourth. However, the coding order is changed to the first&gt;the fourth&gt;the second&gt;the third and the B frame will not be a reference picture for subsequent coding.
A television video signal is an interlace-scanned signal, so that a frame is structured from two fields in which the number of lines is a half and the line position is shifted alternately. There is also a time lag between the fields constituting a frame. On the other hand, for coding, picture data of two fields are merged and then divided and coded into blocks of the predetermined size as picture data of a frame. In an apparatus for picture decoding, pictures are decoded in the coding order, so that decoded results are obtained in the sequential scanning order in block units directing from the upper left to the lower right in the frame. However, in an apparatus for picture decoding, it is necessary to output an interlace-scanned video signal.
Therefore, in an apparatus for picture decoding, it is necessary to convert between sequential scanning in block units and interlace scanning in pixel units. When the B frame is included, it is necessary to reorder the frames so as to reorder to the normal display order.
A conventional apparatus for picture decoding is described in, for example, the 1994 IEICE (Institute of Electronics, Information and Communication Engineers) Spring Conference, C-659 (Proceeding 5, p. 227) or ISSCC94 (1994 IEEE International Solid-State Circuits Conference)/Session 4/Video and Communication Signal Processors/Paper WP4.4. The conventional apparatus for picture decoding consists of a buffering step of writing coded data to be inputted in the coded data buffer once by the input clock, a decoding step of reading and decoding the coded data from the coded data buffer in the predetermined timing and by the decoding clock and writing the decoded picture data in a frame memory having a capacity of several frames once, and a display step of reading the decoded picture data from the frame memory by executing scanning conversion and frame reordering and displaying and outputting it as a digital video signal according to the predetermined display clock. Furthermore, when the decoding data is P frame data or B frame data, the decoding step reads the reference picture data on the reference picture from the frame memory so as to execute motion compensation.
The input clock is a transmission clock itself for digital broadcasting. The display clock relates to the sampling frequency of a digital video signal and is set to a standard value of 13.5 MHz or 27 MHz. The decoding clock is set to a frequency at which the decoding of coded data of each frame can be finished always within the one-frame period even in consideration of variations in the processing amount necessary for decoding coded data of each frame. The processing amount required for decoding coded data of each frame generally varies according to the coding system by which the frame is coded, that is, the I frame, the P frame, or the B frame. The processing amount also varies according to the amount of coded data of the frame. The decoding clock may be set independently of the input clock or the display clock and may be set to a frequency at the predetermined ratio to the display clock. In either case, the decoding step and the display step are performed independently and asynchronously with each other. Furthermore, buffering step of coded data is also necessary and this operation is asynchronous with the memory access operation of the decoding step or the display step. Therefore, an arbitration function for arbitrating the memory access right is essential. It is generally necessary to stop the decoding step during the arbitration period and it is necessary to set the decoding clock slightly higher beforehand so as to process coded data of one frame during the one-frame period excluding the arbitration period.
A conventional apparatus for picture decoding is an apparatus corresponding to a current TV set of the 525/60 system used in USA and Japan, and picture data of one frame consists of data of a luminance signal and two kinds of chrominance signals, and the luminance signal consists of 720 horizontal pixels and 480 vertical lines, and the two kinds of chrominance signals consist of 360 pixels and 240 lines in which the resolution is 1/2 times of that of the luminance signal in both of the horizontal and vertical directions. Furthermore, in a conventional apparatus for picture decoding, four dynamic RAMs of the 256k.times.16 bits (4M bits) configuration are used and for the total capacity of 16M bits, 2 frames for storing picture data on the reference picture necessary for decoding and 1.5 frames necessary for interlace conversion in the display step, that is, 3.5 frames in total (about 4M bits.times.3.5=14M bits) can be used as a frame memory area and about 2M remaining bits can be used as a buffering area for coded data. The data bus reads or writes coded data or picture data 64 (16.times.4) bits in length and 40 MHz is selected as a decoding clock frequency.